1. Field of the Invention
The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to the protection of NMOS transistors by low capacitance ESD protection devices in conjunction with silicone controlled rectifiers (SCRs).
2. Description of the Related Art
The protection of integrated circuits from electrostatic discharge (ESD) is a subject which has received a lot of attention from circuit designers because of the serious damage that ESD can wreak as device dimensions are reduced. Workers in the field and inventors have proposed many solutions, many trying to solve the problem of protecting sub-micron (1 micron=1 xcexcm =10xe2x88x926 meter) devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The main thrust of ESD protection for MOS devices is focused on the snapback breakdown of the NMOS transistor under high field strengths in conjunction with pnp and npn bipolar transistors, which together form a silicon controlled rectifier (SCR). Unwanted as this SCR normally is, it can safely discharge dangerous ESD voltages once triggered by the companion NMOS transistor as long as this trigger voltage is low enough to prevent gate oxide breakdown of the MOS devices which it is designed to protect. With a conventional approach to NMOS design it is hard to design a low capacitance ESD protection device for radio frequency (RF) applications. The below described invention provides a unique solution to ESD protection which has not been proposed in the related art.
U.S. Patents which relate to ESD protection of integrated circuits are:
U.S. Pat. No. 5,872,379 (Lee) describes a low voltage turn-on SCR to provide protection to the input and output circuitry of an integrated circuit during an ESD event.
U.S. Pat. No. 5,811,856 (Lee) discloses an input protection circuit which adds a P+ diffusion adjacent to the emitter of a field device to make the base resistance of each of the field devices approximately equal thus conducting the ESD voltage simultaneously and with equal currents.
U.S. Pat. No. 5,898,205 (Lee) presents an ESD protection circuit which utilizes the insertion of a capacitor in the line between an operating potential bus and the negative power source bus.
U.S. Pat. No. 6,066,879 (Lee) describes an ESD protection circuit which adds a P+ diffusion into the NMOS drain side to build an SCR. A very low snapback voltage of 2 V is achieved.
U.S. Pat. No. 5,753,380 (Ker et al.) provides a modified PTLSCR and NTLSCR for protection of the supply voltage and output pad of an output buffer. The invention requires a smaller layout area than conventional CMOS output buffers with ESD protection.
U.S. Pat. No. 5,753,381 (Ker et al.) is similar to U.S. Pat. No. 5,753,380 above but includes bypass diodes.
It should be noted that none of the above-cited examples of the related art provide for a small protection device and a very low capacitance which could pass a high ESD voltage.
It is an object of the present invention to provide protection for MOS circuits from high ESD voltages by the use of an ESD protection device which is small by virtue of an inherent low capacitance.
It is another object of the present invention to provide an ESD protection device which is particularly well suited for radio frequency (RF) applications.
These and many other objects have been achieved by arranging for an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P+ diffusion. Together they not only form a diode but also form part of a parasitic pnp bipolar transistor which is part of two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which is arranged to have its drain (an N+ diffusion) close to the N-well but without making contact with it. The drain and the P+ diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P+ diffusion, acting as a guard ring, is located on either side of each source (N+ diffusion) and together are coupled to a reference potential (typically ground). An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P+ diffusion ultimately turn on both SCRs, triggered via the above mentioned diode, and conduct the ESD current safely from the chip pad to the source and ground. The MOS circuits connected to the chip pad are thus protected from dangerous ESD voltages.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.
Note that the figures herein illustrate vertical cross sections of devices and that the devices extend laterally (into and/or out of the page) in a manner appreciated by those skilled in the art.